Tuesday, June 7, 2016 at 9:54 pm #225910
This forum is being created to discuss the Questions and Solutions of the Exam Paper of Electronics and Communication branch PHD entrance test being conducted by Punjab University Chandigarh. It is a sincere request to help each other out by giving correct solutions to the questions asked.
Tuesday, June 7, 2016 at 10:00 pm #225911
Q1. 11001, 1001, 111001 correspond to the 2’s complement representation of following set of numbers:
(a) 25, 9 and 57
(b) -6, -6 and -6
(c) -7, -7 and -7
(d) -25, -9 and -57.
Answer as per answer key of PU PHD-2015 is choice C.
However as per my calculation 2’s complement of 11001 = (11001+1)’ = (11010)’ = 00101 = -5,
2’s complement of 1001 = (1001+1)’ = (1010)’ = 0101 = -5
2’s complement of 111001 = (111001+1)’ = (111010)’ = 000101 = -5
Hence I feel answer as per answer key is incorrect.
Tuesday, June 7, 2016 at 10:06 pm #225912
Q2. The output F1F2 for given figure is :
(a) X0 X1 X2
(b) X0 + X1 + X2
Answer as per answer key of PU PHD-2015 is choice D, which is correct.
F1 = D0 + D2 + D4 + D6 = X0′
F2= D1 + D3 + D5 + D7 = X0
Hence F1 F2 = 0
Tuesday, June 7, 2016 at 10:09 pm #225913
Q3. The network shown in Fig 2 implements :
(a) NOR gate
(b) NAND gate
(c) XOR gate
(d) XNOR gate
Answer as per answer key of PU PHD-2015 is choice B, explanation for which I am still looking out for. If anyone can help may please post in the comment about the explanation.
Tuesday, June 7, 2016 at 10:15 pm #225914
Q4. The Mod-Number of the Asynchronous counter shown in Fig 3 is :
Answer as per answer key of PU PHD-2015 is choice A, which seems to be correct.
The counter will be reset to initial state of 0, as and when both Q3 and Q4 reach a state of 1, which will happen at the count of 11000. 11000 is binary equivalent of decimal 24. Hence its a Mod-24 Counter.
Further questions will be keyed in soon, please keep checking back for the same. Happy preparations for PU PHD Entrance Exam 2016, all the best….
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